a. The Field of the Invention
This invention relates to the field of integrated circuit manufacturing. In particular, the invention relates to the concepts and implementation techniques to make fast and efficient integrated circuit layout correction and verification possible.
b. Description of Related Art
In designing an integrated circuit (IC), engineers typically rely upon computer simulation tools to help create a circuit schematic design consisting of individual devices coupled together to perform a certain function. To actually fabricate this circuit in a semiconductor substrate the circuit must be translated into a physical representation, or layout, which itself can then be transferred onto the silicon surface. Again, computer aided design (CAD) tools assist layout designers in the task of translating the discrete circuit elements into shapes which will embody the devices themselves in the completed IC. These shapes make up the individual components of the circuit, such as gate electrodes, field oxidation regions, diffusion regions, metal interconnections, and so on.
The software programs employed by these CAD systems are usually structured to function under a set of predetermined design rules in order to produce a functional circuit. Often, these rules are determined by certain processing and design limitations. For example, design rules may define the space tolerance between devices or interconnect lines so as to ensure that the devices or lines do not interact with one another in any unwanted manner. Design rule limitations are frequently referred to as critical dimensions. A critical dimension of a circuit is commonly defined as the smallest width of a line or the smallest space between two lines. Consequently, the critical dimension determines the overall size and density of the IC. In present IC technology, the smallest critical dimension for state-of-the-art circuits is approximately 0.25 microns for line widths and spacings.
Once the layout of the circuit has been created, the next step to manufacturing the integrated circuit (IC) is to transfer the layout onto a semiconductor substrate. Optical lithography is a well known process for transferring geometric shapes onto the surface of a silicon wafer. The optical lithography process generally begins with the formation of a photoresist layer on the top surface of a semiconductor wafer. A mask having fully light non-transmissive opaque regions, which are usually formed of chrome, and fully light transmissive clear regions, which are usually formed of quartz, is then positioned over the photoresist coated wafer. Light is then shone on the mask via a visible light source or an ultra-violet light source. The light is focused to generate a reduced mask image on the wafer typically using an optical lens system which contains one or several lenses, filters, and or mirrors. This light passes through the clear regions of the mask to expose the underlying photoresist layer, and is blocked by the opaque regions of the mask, leaving that underlying portion of the photoresist layer unexposed. The exposed photoresist layer is then developed, typically through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is a semiconductor wafer coated with a photoresist layer exhibiting a desired pattern which defines the geometries, features, lines and shapes of that layer. This pattern can then be used for etching underlying regions of the wafer.
Besides the aforementioned design rules, the resolution value of the exposure tool used in optical lithography also places limits on the designers of integrated circuit layouts. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose onto the wafer. Currently, the resolution for most advanced optical exposure tools is around 0.25 micron. As the critical dimensions of the layout become smaller and approach the resolution value of the lithography equipment, the consistency between the mask and the actual layout pattern developed in the photoresist is significantly reduced. Specifically, it is observed that differences in pattern development of circuit features depends upon the proximity of the features to one another.
With these limitations on IC design in mind, we note the data describing an IC pattern is usually represented in a condensed hierarchical fashion such as in a GDS-II data file. At the higher levels of pattern representation hierarchy, features are represented in a conceptual manner. For instance, a memory array may be described as having a given cell repeated for a certain number of rows and columns. The next lower level in the hierarchy might describe the basic memory cell, comprised of subcells A and B. Finally, at the lowest level, the most primitive subcells contain geometric primitives-rectangles and polygons. In order to generate a physical mask, the hierarchical data must first be flattened, enumerating every geometric instance described in the hierarchy. Flattening of the hierarchy typically results in several orders of magnitude increase in the size of data storage required to represent the pattern.
Since flattening the hierarchy results in such a large increase in the size of the file representing a given IC design, it is desirable to flatten the hierarchy at the latest point in the manufacture of a mask, which, in the best case, is at the time the mask design is loaded into the EB machine prior to physical manufacture. Currently however, this flattening process takes place at an earlier stage in the production of masks for some complicated IC""s. This is because the original mask design for a complicated IC is typically manipulated after the original design is completed in order to perform one of a number of operations on the design. These operations are performed because of the precision needed in the masks for complicated IC""s as the critical dimensions of these IC""s approach the resolution limits of optical lithography. Currently, these operations require some sort of flattening of the original design data in order to be performedxe2x80x94resulting in an earlier than desired flattening of the design data. These operations include the performance of logical operations, the generation of optical proximity corrections, the generation of phase shifting masks, and the design rule checking of masks that have undergone these operations.
In particular, nearly all modem integrated circuits of even limited complexity require that the original mask design be corrected for optical proximity effects in order that the desired image be accurately reproduced on a wafer after photolithography. Proximity effects occur when very closely spaced pattern features are lithographically transferred to a resist layer on a wafer. The light waves passing through the closely spaced features interact and, as a result, distort the final transferred pattern features. Another problem that occurs when feature sizes and spacing approach the resolution limit of the lithographic tool is that corners (concave and convex) tend to overexpose or underexpose due to a concentration or scarcity of energy at each of the corners. Other types of problems, such as over- or under-exposure of small features when large and small features are transferred from the same mask pattern, also occur.
Numerous methods have been developed to overcome the proximity effect problem. These methods include: precompensating mask line widths, varying photoresist layer thicknesses, using multi-layer photoresist processes, using electron beam imaging in conjunction with optical imaging, and finally, adding additional features to the original mask pattern to compensate for proximity effects. This last method is known as xe2x80x9cOptical Proximity Correctionxe2x80x9d (OPC).
The additional features that are added to the original mask when OPC is utilized are typically sub-resolution (i.e. have dimensions less than the resolution of the exposure tool) and thus do not transfer to the resist layer. Instead, they interact with the original pattern so as to improve the final transferred pattern and compensate for proximity effects.
Currently there are several known OPC software implemented products available that adjust mask definitions to include OPC features. However, thus far, the available products have a number of limitations in terms of correctness, speed, data volume, and verification of the resultant OPC corrected mask design. For, the current products do not maintain the true hierarchical data format of the original mask design when the OPC features are added to the mask design. These products must first expand the original mask design to some type of a flattened data format prior to compensating by adding correction features. This causes the size of the resultant corrected design data file to increase severalfold, and thus slow down the process of OPC. Further, and more importantly, because they do not maintain the original true hierarchical data format of the mask design, it is extremely difficult and time consuming to verify currently known OPC corrected masks using conventional verification tools which require the same hierarchical data format as the original mask.
Therefore, what is desired is a method and apparatus for OPC correcting integrated circuit mask designs that solves the aforementioned problems of currently known systems with respect to correctness, speed, data volume, and verification of results.
As discussed above, currently known systems for the correction of and performance of logical operations on integrated circuit design layouts are not capable of preserving the original hierarchy of the design. This leads to several problems including a large increase in data, a reduction in processing speed, and the loss of the ability to quickly check processed designs for correctness using conventional verification tools.
Accordingly, in one embodiment of the present invention a method for the correction of integrated circuit layouts for optical proximity effects which maintains the hierarchy of the original layout is provided. The correction method comprises providing a hierarchically described integrated circuit layout as a first input, and a particular set of correction criteria as a second input. The integrated circuit layout is then analyzed to identify features of the layout which meet the provided particular correction criteria. After the areas on the mask which need correction have been identified, optical proximity correction data is generated in response to the particular set of correction criteria. Finally, a first program data is generated which stores the generated optical proximity correction data in a hierarchical structure that corresponds to the hierarchical structure of the integrated circuit layout.
In various alternative embodiments of the method, the generated first program data is stored on a computer readable media such as a hard disk drive or a server, and the integrated circuit layout is described by a GDS-II data file or other hierarchical description of the data. In another instance of the above embodiment, the first program data may also be described by a GDS-II data file or other hierarchical description of the data.
In further characterizations of the above method, the generated optical proximity correction data comprises data corresponding to the addition of serif features to the layout, and data corresponding to the correction of transistor gates. In a further embodiment of the above method, the particular set of correction criteria comprises a means for specifically identifying transistor gates in the layout. This instance is further characterized wherein the generated optical proximity correction data may comprise data corresponding to the addition of hammerhead features to the line ends of transistors or wires.
In an alternate embodiment, the method is further characterized by the additional step of combining the first program data with the data describing the integrated circuit mask to produce a second program data that describes a first corrected mask. This embodiment can be further characterized by adding another step which includes flattening the second program data to produce a third program data, and utilizing the third program data to produce an optically corrected lithographic mask.
This embodiment can be further characterized by the addition of a step of providing the second program data to a design rule checker to determine whether the first corrected layout falls within a set of design rules associated with the integrated circuit.
In another instance, this embodiment can be further characterized by the additional steps of providing a set of providing a set of layout accuracy parameters and comparing the first corrected layout to the design accuracy parameters. These added steps further include providing a model based correction means for correcting all areas of the layout in accordance with a particular set of design accuracy rules and applying the model based correction means to the first corrected layout to produce a second corrected layout such that the second corrected layout falls within the set of layout accuracy parameters.
This embodiment can be further characterized by adding the steps of providing the second corrected layout to a design rule checker, operating the design rule checker, and determining whether the second corrected layout falls within a set of design rules associated with the integrated circuit. Alternatively, the above embodiment can be further characterized wherein the step of comparing the first corrected layout to the design accuracy parameters further comprises providing the second program data to a checker device which produces a simulated image of the exposure that the first corrected layout would produce, providing the actual image of the exposure that was designed for the integrated circuit, and measuring the difference between the simulated image and the actual image.
In another instance, the method may also be characterized in that the step of generating the first program may further include generating a plurality of delta planes corresponding to the plurality of cells. In this embodiment, each delta plane comprises data representative of the difference between a correction plane of the cell corresponding to the delta plane and the delta planes corresponding to the children cells of the cell corresponding to the delta plane. In this instance, the correction plane for each cell comprises data that would generate an output data equal to a corrected design for the cell if the correction plane were applied to the flattened cell data.
An alternative embodiment of the basic method claim is also provided. This alternative provides for the steps of providing the integrated circuit layout as a first input and providing a particular set of correction criteria as a second input. Other steps include compiling the hierarchical tree structure, wherein compiling comprises generating a first correction layer for each cell of the plurality of cells in the hierarchical tree structure in response to the particular set of correction criteria. Also included is linking the hierarchical tree structure, wherein linking comprises modifying the correction layer of each cell to generate a delta plane for each cell such that the delta plane of each cell accounts for interaction between each of the cell""s child cells and interaction between the cell""s primitive geometry and each of the cell""s child cells. Lastly, a first program data comprising the delta planes is provided, wherein the first program data is configured hierarchically such that it corresponds to the hierarchical tree structure of the integrated circuit layout.
In an alternate embodiment of this method an additional limitation is added to the above method wherein for each cell in the hierarchical tree structure the sum of the delta plane of the cell and the delta planes of the cell""s child cells comprises a correction plane of the cell wherein the correction plane for the cell comprises data that would generate an output data equal to a corrected design for the cell if the correction plane were applied to the flattened cell data. Other variations of this alternate method are similar to those discussed above with respect to the main method.
Lastly, the method steps of the above embodiments may in one instance be performed by a computer running a program which implements these steps wherein the program is stored on any appropriate computer storage media such as a hard disk drive or server.
The present invention, as summarized above with respect to method steps, may be alternatively characterized as an apparatus for the correction of integrated circuit layouts for optical proximity effects which maintains the hierarchy of the original layout. The apparatus includes, in one embodiment, a first input that receives the integrated circuit layout, a second input that receives a particular set of correction criteria, and a resource that analyzes the integrated circuit layout and identifies features that meet the particular set of correction criteria. Also provided is a resource that generates optical proximity correction data in response to the particular set of correction criteria for the features that meet the particular set of correction criteria and a resource that provides a first program data wherein the first program data comprises the optical proximity correction data configured in a hierarchical structure that corresponds to the hierarchical structure of the integrated circuit layout.
The features discussed above with respect to the method embodiment apply as well with respect to the apparatus embodiment. For instance, the apparatus embodiment can be altered to provide for the addition of serifs and transistor gate corrections to the correction data, and provide for a particular set of correction criteria which comprises a means for specifically identifying transistor gates.
In an alternate embodiment, the apparatus comprises an additional resource that combines the first program data with data describing the integrated circuit mask to provide a second program data that describes a first corrected layout. This embodiment can be further characterized by the addition of a resource that flattens the second program data to produce a third program data, and a resource that utilizes the third program data to produce an optically corrected lithographic mask. This embodiment can be further altered by the provision of a design rule checker which determines whether the first corrected layout falls within a set of design rules associated with the integrated circuit.
In another embodiment, still further elements are added, such as for instance, a third input that receives a set of layout accuracy parameters and a resource that compares the first corrected layout to the design accuracy parameters. Also provided is a resource that provides a model based correction means for correcting all areas of the layout in accordance with a particular set of design accuracy rules and a resource that applies the model based correction means to the first corrected layout to produce a second corrected layout such that the second corrected layout falls within the set of layout accuracy parameters. This embodiment can be further characterized by the addition of a design rule checker that receives the second corrected mask and determines whether the second corrected layout falls within a set of design rules associated with the integrated circuit.
This embodiment can be still further characterized by the addition of a resource that provides the second program data to a checker device which produces a simulated image of the exposure that the first corrected layout would produce. Also provided in this instance is a resource that provides the actual image of the exposure that was designed for the integrated circuit and a resource that measures the difference between the simulated image and the actual image.
Lastly, the apparatus of the above embodiments may in one instance be represented by a computer program product which comprises, in one instance, a computer usable medium having a computer readable program code embodied therein for causing a computer to generate optical proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical structure.
Although many details have been included in the description and the figures, the invention is defined by the scope of the claims. Only limitations found in those claims apply to the invention.